A semiconductor integrated circuit device is tested, before its shipment, as to whether or not its internal logic circuit or memory circuit may be in normal operation. FIG. 4 depicts a block diagram showing a conventional semiconductor integrated circuit device 160. Referring to FIG. 4, in a conventional test method, after a test input signal is applied from an external tester 200 to the inside of the semiconductor integrated circuit device 160 and a clock signal is generated, a comparison circuit 120 determines whether or not the output signal of a device under test 150 coincides with an ideal output signal. The frequency of the clock signal, which can be generated by the tester 200 and strobed from the outside into the inside of the semiconductor integrated circuit device 160, is generally 100 MHz or less. Therefore, it is necessary to conduct a test using a clock signal slower than the clock signal used during the normal operation of the semiconductor integrated circuit device 160. Faulty operations that may be detected with this test scheme are normally those not dependent on the operational speed, examples of which include open faults and short faults.
Recently, an at-speed test scheme is coming into use, in which a clock signal and a test input signal are generated within the semiconductor integrated circuit device 160, and are in operation at a rated frequency actually employed to observe the behavior. For example, Patent Document 1 shows a scheme in which a clock signal is generated by a clock signal generator (not shown in the drawing) provided in the semiconductor integrated circuit device 160, and in which the test input signal is generated by a BIST (Built-In Self Test) circuit (not shown in the drawing) provided in the inside of the semiconductor integrated circuit device 160. In this case, the BIST circuit generates the input signal, every clock cycle, the generated clock signal is delivered to a circuit under test 150, and the comparison circuit 120 compares an output signal of the circuit under test 150 to the ideal output signal to determine whether the output signal is normal or not. This scheme allows to detect a fault that depends on the operating speed, for example, such a fault in which the operating speed is slower than the rated speed.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2006-073081A    [Patent Document 2] JP Patent Kokai Publication No. JP-P2001-318730A